After completing my first BeagleBone Black + FPGA project and tutorial where I drove a single 32×32 RGB LED matrix, I decided it was time to go bigger. The result is the project shown below—a 3 x 2 matrix of 32×32 RGB LED panels. That’s 6,144 RGB LEDs or 18,432 LED chips—each of which can be controlled with 12-bit color at a refresh rate of 200Hz. Let’s take a closer look at the steps required to move from driving one panel to driving six panels.
Here is a video on YouTube of the six panel project in action.
The first step was to build a frame to mount the panels. I used a set of calipers to locate each mounting hole and determine the clearance required for each of the connectors on the LED panels. I drew the frame using the free front panel design software from frontpanelexpress.com. I added holes to mount the BeagleBone Black and a 60W +3.3V power supply. Once I had the basic layout completed, I decided to use 20mm x 40mm aluminum extrusions to give the panel some depth to hold the electronics behind the frame and panels. I finally had the frame and two wall mounting brackets fabricated at frontpanelexpress.com.
The Verilog needed some changes to drive the increased number of panels:
- The number of clock cycles used to shift each set of RGB data bits into the panels was reduced from 3 to 2.
- The frame buffer memories were increased from 2 x 1024 x 12 bits to 2 x 8192 x 12 bits.
- To maintain my 12-bit color depth and 200Hz refresh rate, the clock used to drive the panel refresh logic was bumped to 25MHz from 10MHz.
- I added support for global dimming so that the overall brightness of the panel could be controlled without affecting the color depth of the panel.
These changes were relatively quick and easy to make. A few simulations and a run through the Xilinx ISE tools yielded a new bit file ready to drive up to six panels.
The Xilinx Spartan 6 LX9 has enough block RAM to drive up to 16 panels. By bumping the clock to 30MHz from 25MHz, 8 panels could be driven. If the refresh rate were dropped to 100Hz, 16 panels could be driven. If more I/Os were available on the LogiBone FPGA board, 16 panels could be driven at 200Hz. All with 12-bit color.
Most of the software used to display patterns only required changing the display width and height defines and the write levels function to port to the larger display. The exception was the Perlin noise routine. In a floating point implementation with all compiler optimization disabled, the Perlin noise routine could only drive about 1.5 panels. I converted the Perlin noise routine to use fixed point arithmetic and turned on -O3 compiler optimizations. With these changes, the BeagleBone Black can perform the approximately 600,000 3D Perlin noise operations required to update the 6144 pixels fifty times a second at about 50% CPU utilization.
Below are some photos and here is a video of the six panel project in action.
Source code for the FPGA, the software, and the frame design are available in my github repository.